1use super::cache::Initializer;
2use super::features_macro;
3
4use core::arch::x86_64::{__cpuid, __cpuid_count, CpuidResult};
5use core::mem;
6
7features_macro! {
8 @TARGET: x86;
9 @CFG: any(target_arch = "x86", target_arch = "x86_64", doc);
10 @MACRO_NAME: is_x86_feature_detected;
11 @MACRO_ATTRS: #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))]
12 @FEATURE: tsc: "tsc": "system has a timestamp counter accessible through `rdtsc`";
13 @FEATURE: msr: "msr": "system supports reading and writing model specific registers through `rdmsr` and `wrmsr`";
14 @FEATURE: apic: "apic": "system has an APIC";
15 @FEATURE: cx16: "cx16": "system support 16-byte atomics";
16 @FEATURE: pcid: "pcid": "system supports PCIDs in page tables";
17 @FEATURE: x2apic: "x2apic": "APIC supports x2APIC features";
18 @FEATURE: tsc_deadline: "tsc_deadline": "local APIC timer supports TSC deadline mode";
19 @FEATURE: xsave: "xsave": "system supports the `xsave` instruction";
20 @FEATURE: xsaveopt: "xsaveopt": "system supports the `xsaveopt` instruction";
21 @FEATURE: xsavec: "xsavec": "system supports the `xsavec` instruction";
22 @FEATURE: hypervisor: "hypervisor": "system is running in a hypervisor";
23 @FEATURE: arat: "arat": "local APIC timer continues counting while sleeping";
24 @FEATURE: intel_thread_director: "intel_thread_director": "system supports Intel Thread Director";
25 @FEATURE: fsgsbase: "fsgsbase": "system supports writing to the `fs` and `gs` registers from userspace";
26 @FEATURE: tsc_adjust: "tsc_adjust": "system supports adjusting TSC value per-core";
27 @FEATURE: smep: "smep": "system supports Supervisor Mode Execution Prevention";
28 @FEATURE: invpcid: "invpcid": "system supports invalidating an entire PCID from the TLB";
29 @FEATURE: smap: "smap": "system supports Supervisor Mode Access Prevention";
30 @FEATURE: la57: "la57": "system supports 57-bit virtual addresses";
31 @FEATURE: rdpid: "rdpid": "system supports reading OS core ID from `IA32_TSC_AUX`";
32 @FEATURE: hybrid: "hybrid": "system has AMP";
33 @FEATURE: lass: "lass": "system supports trapping access based on MSB of address";
34 @FEATURE: nmi_src: "nmi_src": "system supports reporting source of NMI exceptions";
35 @FEATURE: xsave_x87: "xsave_x87": "system supports saving x87 registers with `xsave`";
36 @FEATURE: xsave_sse: "xsave_sse": "system supports saving SSE registers with `xsave`";
37 @FEATURE: xsave_avx: "xsave_avx": "system supports saving AVX registers with `xsave`";
38 @FEATURE: xsave_avx512_opmask: "xsave_avx512_opmask": "system supports saving AVX512 opmask registers with `xsave`";
39 @FEATURE: xsave_avx512_zmm_hi256: "xsave_avx512_zmm_hi256": "system supports saving upper 256 bits of `zmm0` through `zmm15` with `xsave`";
40 @FEATURE: xsave_avx512_zmm_hi16: "xsave_avx512_zmm_hi16": "system supports saving `zmm16` through `zmm31` with `xsave`";
41 @FEATURE: xsave_pkru: "xsave_pkru": "system supports saving PKRU register with `xsave`";
42 @FEATURE: xsave_amx_cfg: "xsave_amx_cfg": "system supports saving AMX `tilecfg` register with `xsave`";
43 @FEATURE: xsave_amx_tile_data: "xsave_amx_tile_data": "system supports saving AMX `tmm0` through `tmm7` registers with `xsave`";
44 @FEATURE: xsave_apx_gpr: "xsave_apx_gpr": "system supports saving `r16` through `r31` GPRs with `save`";
45 @FEATURE: nx: "nx": "page tables support no-execute bit";
46 @FEATURE: pdpe1gb: "pdpe1gb": "page tables support 1 GiB huge pages";
47 @FEATURE: rdtscp: "rdtscp": "system supports `rdtscp` instruction to read TSC and `IA32_TSC_AUX`";
48 @FEATURE: extapic: "extapic": "APIC support Extended APIC Space";
49 @FEATURE: invlpgb: "invlpgb": "system supports `invlpgb` instruction";
50}
51
52pub(super) fn detect() -> Initializer {
53 let mut initializer = Initializer::new();
54
55 let (max_basic_leaf, _vendor_id) = {
56 let CpuidResult {
57 eax: max_basic_leaf,
58 ebx,
59 ecx,
60 edx,
61 } = __cpuid(0);
62 let vendor_id: [[u8; 4]; 3] = [
63 u32::to_ne_bytes(ebx),
64 u32::to_ne_bytes(edx),
65 u32::to_ne_bytes(ecx),
66 ];
67 let vendor_id: [u8; 12] = unsafe { mem::transmute(vendor_id) };
69 (max_basic_leaf, vendor_id)
70 };
71
72 if max_basic_leaf < 1 { return initializer; }
73
74 let CpuidResult {
75 ecx: proc_info_ecx,
76 edx: proc_info_edx,
77 ..
78 } = __cpuid(0x0000_0001);
79
80 let thermal_power_eax = if max_basic_leaf >= 6 {
81 let CpuidResult { eax, .. } = __cpuid(0x0000_0006);
82 eax
83 } else {
84 0 };
86
87 let (extended_features_eax, extended_features_ebx, extended_features_ecx, extended_features_edx) = if max_basic_leaf >= 7 {
88 let CpuidResult { eax, ebx, ecx, edx } = __cpuid(0x0000_0007);
89 (eax, ebx, ecx, edx)
90 } else {
91 (0, 0, 0, 0) };
93
94 let extended_features_1_eax = if extended_features_eax >= 1 {
95 let CpuidResult { eax, .. } = __cpuid_count(0x0000_0007, 1);
96 eax
97 } else {
98 0 };
100
101 let (_xsave_xcr0_high, xsave_xcr0_low) = if proc_info_ecx & (1 << 26) != 0 {
102 let CpuidResult { eax, edx, .. } = __cpuid_count(0x0000_000d, 0);
103 (edx, eax)
104 } else {
105 (0, 0)
106 };
107
108 let xsave_feature = if proc_info_ecx & (1 << 26) != 0 {
109 let CpuidResult { eax, .. } = __cpuid_count(0x0000_000d, 1);
110 eax
111 } else {
112 0
113 };
114
115 let CpuidResult {
116 eax: extended_max_basic_leaf,
117 ..
118 } = __cpuid(0x8000_0000);
119
120 let (extended_proc_info_ecx, extended_proc_info_edx) = if extended_max_basic_leaf >= 1 {
121 let CpuidResult { ecx, edx, .. } = __cpuid(0x8000_0001);
122 (ecx, edx)
123 } else {
124 (0, 0)
125 };
126
127 let paging_features_ebx = if extended_max_basic_leaf >= 8 {
128 let CpuidResult { ebx, .. } = __cpuid(0x8000_0008);
129 ebx
130 } else {
131 0
132 };
133
134 {
135 let mut enable = |value: u32, bit: u32, feature: Feature| {
136 if value & (1 << bit) != 0 {
137 initializer.set(feature);
138 }
139 };
140
141 enable(proc_info_edx, 4, Feature::tsc);
142 enable(proc_info_edx, 5, Feature::msr);
143 enable(proc_info_edx, 9, Feature::apic);
144 enable(proc_info_ecx, 13, Feature::cx16);
145 enable(proc_info_ecx, 17, Feature::pcid);
146 enable(proc_info_ecx, 21, Feature::x2apic);
147 enable(proc_info_ecx, 24, Feature::tsc_deadline);
148 enable(proc_info_ecx, 26, Feature::xsave);
149 enable(xsave_feature, 0, Feature::xsaveopt);
150 enable(xsave_feature, 1, Feature::xsavec);
151 enable(proc_info_ecx, 31, Feature::hypervisor);
152 enable(thermal_power_eax, 2, Feature::arat);
153 enable(thermal_power_eax, 23, Feature::intel_thread_director);
154 enable(extended_features_ebx, 0, Feature::fsgsbase);
155 enable(extended_features_ebx, 1, Feature::tsc_adjust);
156 enable(extended_features_ebx, 7, Feature::smep);
157 enable(extended_features_ebx, 10, Feature::invpcid);
158 enable(extended_features_ebx, 20, Feature::smap);
159 enable(extended_features_ecx, 16, Feature::la57);
160 enable(extended_features_ecx, 22, Feature::rdpid);
161 enable(extended_features_edx, 15, Feature::hybrid);
162 enable(extended_features_1_eax, 6, Feature::lass);
163 enable(extended_features_1_eax, 20, Feature::nmi_src);
164 enable(xsave_xcr0_low, 0, Feature::xsave_x87);
165 enable(xsave_xcr0_low, 1, Feature::xsave_sse);
166 enable(xsave_xcr0_low, 2, Feature::xsave_avx);
167 enable(xsave_xcr0_low, 5, Feature::xsave_avx512_opmask);
168 enable(xsave_xcr0_low, 6, Feature::xsave_avx512_zmm_hi256);
169 enable(xsave_xcr0_low, 7, Feature::xsave_avx512_zmm_hi16);
170 enable(xsave_xcr0_low, 9, Feature::xsave_pkru);
171 enable(xsave_xcr0_low, 17, Feature::xsave_amx_cfg);
172 enable(xsave_xcr0_low, 18, Feature::xsave_amx_tile_data);
173 enable(xsave_xcr0_low, 19, Feature::xsave_apx_gpr);
174 enable(extended_proc_info_edx, 20, Feature::nx);
175 enable(extended_proc_info_edx, 26, Feature::pdpe1gb);
176 enable(extended_proc_info_edx, 27, Feature::rdtscp);
177 enable(extended_proc_info_ecx, 3, Feature::extapic);
178 enable(paging_features_ebx, 3, Feature::invlpgb);
179 }
180
181 initializer
182}